Generally, integrated circuits include a complex network of conductive interconnects fabricated on a semiconductor substrate in which semiconductor devices have been formed. Efficient routing of these interconnects requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures.
Within an interconnect structure, conductive vias run perpendicular to the semiconductor substrate and conductive lines run parallel to the semiconductor substrate. According to conventional damascene processing, lines and vias are created within a dielectric layer. A dielectric layer is patterned to create grooves which become lines and holes which become vias. Metal is deposited on the patterned surface such as by electroplating to fill the grooves and holes. Excess is removed, such as by CMP, thereby forming lines along the top of a given dielectric layer, and forming vias which extend below the lines in order to connect to an underlying layer.
Copper or a Cu alloy has recently been preferred to form the conductive interconnects to provide high speed signal transmission between transistors on a complex semiconductor chip. Copper typically requires a barrier layer to prevent it from migrating into, and thereby degrading the insulating capacity of, surrounding dielectric material. As feature sizes continue to decrease in the ongoing development of more and more densely built integrated circuits, the limitations of dielectric damascene and copper are increasingly apparent. For one, smaller feature size of the conductive features generally requires higher aspect ratio, and it is increasingly difficult to fill such features to form void free metal structures. Forming a barrier layer within high aspect features is particularly difficult. Furthermore, as feature sizes continue to decrease, the barrier cannot scale and hence constitutes a greater fraction of any particular feature. Additionally, as the feature dimensions become comparable to the bulk mean free path, the effective resistivity of copper features will increase because of normegligible electron scattering at the copper-barrier interface and at grain boundaries. See Pawan Kapur et al., Technology and Reliability Constrained Future Copper Interconnects—Part 1 Resistance Modeling, 49: 4, IEEE Transactions on Electron Devices 590 (April 2002).
Some challenges associated with copper damascene can be avoided by forming the interconnect structure by an alternate metal using subtractive metal etch (“SME”), as for example is discussed in U.S. Pat. No. 5,512,514 (“Saile”). In SME, a metal layer is deposited, then etched according to one or more patterns to remove all but the interconnect structures. For example, referring to FIG. 1 which represents a prior art integrated circuit according to Saile, an isolation layer 12 overlies a semiconductor substrate 10. A first metal stack is formed by depositing a first metal layer 21, an optional etch stop layer 22; a second metal layer 23, and an anti-reflective coating layer 24. The stack is etched through to isolation layer 12 according to a first mask for first conductive lines, which mask is formed over layer 24 by patterning a first photoresist layer. The stack is then etched through to etch stop layer 22 according to a second mask for first vias, which mask is formed by patterning a second photoresist layer. A dielectric layer 25 is deposited over the exposed substrate and the etched features to fill the voids formed by such etch steps. A second interconnect layer of lines 31, vias 33, and dielectric 35 can be formed by repeating the process. According to this SME process, that portion of such a nth metal stack covered by both n-level masks forms the vias, and results within the nth dielectric layer, self-aligned vias that extend above metal lines.
A problem with forming multi-layered interconnect structure by subtractive metal etch, however, is the difficulty of correctly positioning features in an upper layer such that they align with features in an underlying layer. Alignment is difficult because the underlying features are not visible under the opaque upper metal layer.